(1) Field of the Invention
The present invention relates to the manufacture of ultra large scale integrated (ULSI) circuit chips in general, and in particular, to a method of using a particular intermetal dielectric (IMD) layer and an etch-stop layer with low-k dielectric constant in order to reduce the RC (resistance capacitance) of a dual damascene interconnect.
(2) Description of the Related Art
As the Very Large Scale Integrated (VLSI) circuit technology has been migrating more and more towards Ultra Large Scale Integrated (ULSI) circuit technology, requirements for interconnecting a myriad of devices has been escalating. Specifically, with the ever increasing miniaturization, the requirements for providing a low RC (resistance capacitance) interconnect pattern has been exacerbated by higher aspect ratio submicron vias, contacts and line trenches. As is known in the art, miniaturization directly affects the RC delay of the parasitic capacitance generated by various insulative layers, including the intermetal dielectric (IMD) layers. Hence, it is disclosed later in the embodiments of the present invention a method of reducing the RC delay by employing different dielectric materials and replacing some of the layers, such as the etch-stop layer used in forming damascene structures, with low dielectric constant (low-k) materials.
Dual damascene process is a well-known technique for forming interconnections in semiconductor devices. It is especially well suited for Ultra Large Scale Integrated (ULSI) circuit technology where more and more devices are being packed into the same or smaller areas in a semiconductor substrate. As the feature sizes get smaller, the smaller geometries result in higher electrical resistances, which in turn degrade circuit performance. As will be described more fully later, damascene process provides a more exact dimensional control over small geometries, while copper, as the metallization material, provides better electrical characteristics.
The term `damascene` is derived from a form of inlaid metal jewelry first seen in the city of Damascus. In the context of integrated circuits it implies a patterned layer imbedded on and in another layer such that the top surfaces of the two layers are coplanar. Thus, in semiconductor manufacturing, grooves and holes in appropriate locations in the grooves are formed in an insulating material by etching, which are then filled with metal. Metal in grooves form the horizontal metal line interconnects while the metal in the underlying holes form the vertical connections to the layers of metal interconnects formed in the previous damascene structure.
Thus, in a single damascene semiconductor manufacturing process, incisions, or grooves, are formed in an insulating layer and filled with metal to form conductive lines. Dual damascene takes the process one step further in that, in addition to forming the grooves of a single damascene, hole openings are also formed at appropriate places in the groove further into the insulating layer. The resulting composite structure of grooves and holes are filled with metal. The process is repeated as many times as required to form the multi-level interconnections between metal lines and the holes formed therebetween.
In one approach for a dual damascene process shown in FIG. 1a, two insulating layers (120) and (130) are formed on a substrate (100) with an intervening etch-stop layer (125). Substrate (100) is provided with metal layer (110) and a barrier layer (115). Metal layer can be the commonly used aluminum or copper, while the barrier can be an oxide layer. A desired trench or groove pattern (150) is first etched into the upper insulating material (130) using conventional photolithographic methods and photoresist (140). The etching stops on etch-stop layer (125). Next, a second photoresist layer (160) is formed over the substrate, thus filling the groove opening (150), and patterned with hole opening (170), as shown in FIG. 1b. The hole pattern is then etched into the lower insulating layer (120) as shown in FIG. 1c and photoresist removed, thus forming the dual damascene structure shown in FIG. 1f.
Or, the order in which the groove and the hole are formed can be reversed. Thus, the upper insulating layer (130) is first etched, or patterned, with hole (170), as shown in FIG. 1d. The hole pattern is also formed into etch-stop layer (125). Then, the upper layer is etched to form groove (150) while at the same time the etching transfers the hole pattern in the etch-stop layer into lower insulation layer (120), as shown in FIG. 1e. It will be noted that the etch-stop layer stops the etching of the groove into the lower insulation layer. After the completion of the thusly formed dual damascene structure, both the hole opening and groove opening are filled with metal (180), and any excess material on the surface of the substrate is removed by chemical mechanical polishing, as seen in FIG. 1f.
In prior art, there are various dual damascene processes that are taught. Huang, et al., in U.S. Pat. No. 5,635,423, disclose a simplified dual damascene process for multi-level metallization and interconnection structure. In one embodiment, an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch-stop layer therebetween. A larger opening for a trench is then formed in the second insulative layer while simultaneously extending the via opening through the etch-stop layer and first insulative layer. The trench and via are then simultaneously filled with conductive material.
Yu, et al., propose, in U.S. Pat. No. 5,985,753, a method to manufacture dual damascene using a phantom implant mask, wherein a selected layer is implanted with heavy ions in a pattern having dimensions of a via structure to be formed in a first layer of interlayer dielectric. In a first embodiment, the ions are implanted in an etch-stop layer formed between a first and second layer of interlayer dielectric. In a second embodiment, the ions are implanted in the second layer of interlayer dielectric. Selective etch processes form a trench structure in the second layer of interlayer dielectric and form a via structure in the first layer of interlayer dielectric. The via structure and trench structure are filled with a conductive material.
In another U.S. Pat. No. 6,013,581, Wu, et al., show a method for preventing the occurrence of poisoned trenches and vias in a dual damascene process that includes performing a densification process, such as a plasma treatment, on the surface of the exposed dielectric layer around the openings before the openings are filled with conductive material. The densified surface of the dielectric layer is able to prevent the occurrence of poisoned trenches and vias caused by the outgassing phenomenon.
Liu, et al., of U.S. Pat. No. 6,010,962, on the other hand, teach a method of forming inlaid copper interconnects, but without the attendant dishing that occurs after chemical-mechanical polishing (CMP) of excess copper. This is accomplished by forming a conformal blanket barrier layer in the form of a dome-like structure over the interconnect so that this structure prevents the dishing of the copper metal during CMP.
The present invention teaches the use of different composition of materials for forming a dual damascene structure having an over-all low dielectric constant and reduced RC delay characteristics.